It is well known to those skilled in the art that strained silicon can enhance carrier mobility for both electrons and holes in comparison with bulk silicon. In addition, the degree of mobility enhancement strongly depends on the strain level in the strained silicon layer. Namely, the higher the imposed “tensile” strain, the higher the enhancement on mobility. The most common practice for applying or inducing tensile strain to a silicon layer is through the use of an underlying silicon germanium (SiGe) buffer layer, which is typically a relaxed SiGe layer having a larger lattice constant as compared to bulk silicon. Hence, by increasing the Ge content of the underlying SiGe buffer layer, which in turn increases the lattice constant of the SiGe buffer layer, a higher “tensile” strain can then be imposed to the silicon layer due to a larger lattice mismatch between the two layers.
It is also well known that metal oxide semiconductor field effect transistor (MOSFET) devices fabricated on silicon-on-insulator (SOT) substrates can have up to 25-35% better performance than those built on bulk Si wafers due to lower parasitic capacitance of the source/drain junction, reduced short channel effects and better device isolation. This is reported, for example, in G. G. Shahidi, “SOI Technology for GHz Era”, IBM J. Res. & Dev., Vol. 46, pp. 121-131 (2002). Thus, it is desirable to combine these two effects to generate a strained silicon layer having enhanced carrier mobility on a SiGe-on-insulator (SGOI) substrate to achieve an even higher device performance gain.
However, this prior scheme is faced with two major problems or issues in its attempt to obtain the best device performance from this synergistic combination of strained silicon on SGOI. One issue is the ability to generate a fully relaxed SiGe buffer layer with a high Ge content such that its lattice constant is strictly determined by the value of the Ge content and is independent of its degree of relaxation. Otherwise, the imposed “tensile” strain to the silicon layer would not be as high as desired. Moreover, in the case for a partially relaxed SiGe buffer, the imposed strain could easily fluctuate or change due to subsequent thermal processing or integration steps which is undesirable.
The second issue is the ability to create a near defect-free SGOI substrate with a high Ge content, which is the more difficult problem to address. Although thermally-mixed (TM) SGOI has provided an alternative approach to creating a SGOI substrate, the SiGe layers typically formed on the TM-SGOI wafers are partially relaxed, i.e., about 50 to 65% at best, and have yet to achieve a fully relaxed SiGe layer with greater than 90% relaxation.
In a similar way, the same difficulty has been encountered in preparation of SGOI substrates generated by the alternate SIMOX approach. See, for example, T. Mizuno, et al.,“High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology”, IEDM Tech. Dig., pp. 934-936 (1999).
Recently, it has been demonstrated that a fully relaxed SiGe buffer layer can be transferred to a handle wafer through a wafer bonding technique. See U.S. Pat. No. 6,524,935 to D. F. Canaperi, et al. However, the bonded SGOI wafers prepared from this prior art process still suffer from various bond-induced defects, such as blisters, bubbles, voids, etc., especially for the high Ge content SGOI wafers where the Ge content is larger than 25 atomic (at.) %.